Semiconductors Capabilities

Power Integrity Signoff

Dynamic and static IR drop analysis for full-chip and IP signoff of both digital and analog designs

Power Integrity Signoff

Timing Impact of IR Drop

Timing analysis of critical paths with fast, SPICE-accurate, voltage variability models

Timing Impact of IR Drop

2.5D/3D-IC Electrothermal Signoff

Chip Package System co-design

2.5D/3D-IC Electrothermal Signoff

RTL Power Analysis and Reduction

Analyze, debug and reduce power and rapidly profile vectors for power-efficient RTL

RTL Power Analysis and Reduction

Electromagnetic Analysis for Silicon

High Capacity Electromagnetic Modeling Engine For High-Speed RF and Digital SOCs

Electromagnetic Analysis for Silicon

Electrostatic Discharge (ESD) and Substrate Noise Analysis

Comprehensive reliability analysis and simulation for more robust designs

Electrostatic Discharge (ESD) and Substrate Noise Analysis

Cloud-Native Elastic Compute Architecture

World’s first big data architecture for electronic system design and simulation

Cloud-Native Elastic Compute Architecture

Semiconductors Products

Ansys RedHawk-SC

  • Golden IR-drop signoff verification for digital designs
  • Electromigration reliability signoff
  • Timing impact of dynamic voltage drop aggressors
  • High-capacity cloud-native infrastructure
  • Advanced power analytics and build quality metric
  • Foundry certified for all finFET to 3nm
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Ansys RedHawk-SC Electrothermal

  • RedHawk-SC option for 3D/2.5D chip-package co-analysis
  • Power integrity analysis of coupled chip-package system
  • Thermal simulation
  • Identifies thermal-mechanical stress
  • Comprehensive early prototyping features
  • Integrated with board/system analysis tools
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Ansys Totem

  • Power integrity and noise verification at transistor level
  • Capacity for several million xtor flat
  • Simultaneous simulation of digital and analog blocks
  • Abundant what-if scenarios
  • Incremental analysis
  • Creates IP power models for use with RedHawk-SC
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Ansys PathFinder-SC

  • Electrostatic discharge (ESD) integrity simulation
  • Current density checks
  • Layout level and netlist level analysis
  • Integrated extraction and simulation engine
  • Foundry-certified silicon correlation
  • Capacity to analyze full SoCs
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Ansys Clock FX

Voltage Variability-Aware SOC Clock Jitter Analysis Software

Ansys Clock FX software for IC design performs fast, SPICE-accurate transistor level timing analysis on Clock Trees and Clock Meshes in the design with voltage and temperature variability using a single library model.

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Ansys PowerArtist

  • RTL design-for-power platform
  • Analysis-driven power reduction
  • Physically-aware RTL power budgeting
  • Long vector profiling
  • Direct links to hardware emulators
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Ansys RaptorH

  • Electromagnetic on-silicon modeling
  • Includes gold standard HFSS engine
  • High-capacity and linear multi-CPU scalability
  • S-param and RCLk parasitic extraction
  • Models power grids, clock trees, spirals, MiM/MoM caps, etc.
  • Foundry certified and silicon correlated
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Ansys Exalto

  • RLCk signoff extraction tool (post-LVS)
  • Models electrical, magnetic and substrate coupling
  • Highly reduced lumped-element models
  • Complements digital RC extractors
  • Extract entire SoC power grid in minutes
  • What-if capability with point-and-click GUI
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Ansys VeloceRF

  • Synthesis and modeling of inductors, transformers and transmission lines
  • Creates DRC/DFM clean devices
  • Silicon verified up t0 110GHz
  • S-param and compressed RCLk models
  • Generates parameterized PCell/PyCells
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